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1 features ? low-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) internally organized 131,072 x 8 two-wire serial interface schmitt triggers, filtered in puts for noise suppression bidirectional data transfer protocol 400 khz (2.7v) and 1 mhz (5v) clock rate write protect pin for hardware and software data protection 256-byte page write mode (partial page writes allowed) random and sequential read modes self-timed write cycle (5 ms typical) high reliability ? endurance: 100,000 write cycles/page ? data retention: 40 years 8-lead pdip, 8-lead eiaj soic, 8- lead lap and 8-lead sap packages die sales: wafer form, waffle pack and bumped die description the at24c1024 provides 1,048,576 bits of serial electrically erasable and program- mable read only memory (eepr om) organized as 131,072 wo rds of 8 bits each. the device?s cascadable feature allows up to two devices to share a common two-wire bus. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the devices are available in space-saving 8-lead pdip, 8-lead eiaj soic, 8-lead leadless array (lap) and 8-lead sap packages. in addition, the entire family is available in 2.7v (2.7v to 5.5v) versions. table 1. pin configurations pin name function a1 address input sda serial data scl serial clock input wp write protect nc no connect two-wire serial eeprom 1m (131,072 x 8) at24c1024 rev. 1471n?seepr?12/05 8-lead pdip 1 2 3 4 8 7 6 5 nc a1 nc gnd vcc wp scl sda 8-lead leadless array bottom view 1 2 3 4 8 7 6 5 vcc wp scl sda nc a1 nc gnd 8-lead soic 1 2 3 4 8 7 6 5 nc a1 nc gnd vcc wp scl sda 8-lead sap bottom view vcc wp s cl s da nc a1 nc gnd 1 2 3 4 8 7 6 5
2 at24c1024 1471n?seepr?12/05 figure 1. block diagram absolute maximum ratings* operating temperature..................................?55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .....................................?65 c to +150 c voltage on any pin with respect to ground .................................... ?1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at24c1024 1471n?seepr?12/05 pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negat ive edge clock data out of each device. serial data (sda): the sda pin is bi-directional for se rial data transfer. this pin is open- drain driven and may be wire-ored with any number of other open-drain or open-collector devices. device/addresses (a1): the a1 pin is a device address input that can be hardwired or left not connected for har dware compatibility with other at24c xx devices. when the a1 pin is hardwired, as many as two 1024k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). if the a1 pin is left floating, the a1 pin will be internally pulled down to gnd if th e capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends connecting the a1 pin to gnd. write protect (wp): the write protect input, when connect ed to gnd, allo ws normal write operations. when wp is connected high to v cc , all write operations to the memory are inhib- ited. if the pin is left floating, the wp pin will be internally pulled dow n to gnd if the capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends con- necting the pin to gnd. switching wp to v cc prior to a write operation creates a software write-protect function. memory organization at24c1024, 1024k serial eeprom: the 1024k is internally organized as 512 pages of 256 bytes each. random word addressing requires a 17-bit data word address.
4 at24c1024 1471n?seepr?12/05 table 2. pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. table 3. dc characteristics note: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +2.7v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 1 , scl) 6 pf v in = 0v applicable over recommended operating range from: t ai = ?40 c to +85 c, v cc = +2.7v to +5.5v, t ac = 0 c to +70 c, v cc = +2.7v to +5.5v (unless otherwise noted) symbol parameter test co ndition min typ max units v cc supply voltage 2.7 5.5 v i cc supply current v cc = 5.0v read at 400 khz 2.0 ma i cc supply current v cc = 5.0v write at 400 khz 5.0 ma i sb standby current v cc = 2.7v v in = v cc or v ss 3.0 a v cc = 5.5v 6.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ?0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol output low level v cc = 3.0v i ol = 2.1 ma 0.4 v
5 at24c1024 1471n?seepr?12/05 table 4. ac characteristics (1) notes: 1. ac measurement conditions: r l (connects to v cc ): 1.3 k ? (2.7v, 5v) input pulse voltages: 0.3 v cc to 0.7 v cc input rise and fall times: 50 ns input and output timing reference voltages: 0.5 v cc 2. this parameter is ensured by characterization only. applicable over recommended operating range from t a = ?40 c to +85 c, v cc = +2.7v to +5.5v, c l = 100 pf (unless otherwise noted) symbol parameter test conditions min max units f scl clock frequency, scl 4.5v v cc 5.5v 2.7v v cc 5.5v 1000 400 khz t low clock pulse width low 4.5v v cc 5.5v 2.7v v cc 5.5v 0.4 1.3 s t high clock pulse width high 4.5v v cc 5.5v 2.7v v cc 5.5v 0.4 0.6 s t aa clock low to data out valid 4.5v v cc 5.5v 2.7v v cc 5.5v 0.05 0.05 0.55 0.9 s t buf time the bus must be free before a new transmission can start (2) 4.5v v cc 5.5v 2.7v v cc 5.5v 0.5 1.3 s t hd.sta start hold time 4.5v v cc 5.5v 2.7v v cc 5.5v 0.25 0.6 s t su.sta start setup time 4.5v v cc 5.5v 2.7v v cc 5.5v 0.25 0.6 s t hd.dat data in hold time 0 s t su.dat data in setup time 100 ns t r inputs rise time (2) 0.3 s t f inputs fall time (2) 4.5v v cc 5.5v 2.7v v cc 5.5v 100 300 ns t su.sto stop setup time 4.5v v cc 5.5v 2.7v v cc 5.5v 0.25 0.6 s t dh data out hold time 50 ns t wr write cycle time 10 ms endurance (2) 5.0v, 25 c, page mode 100k write cycles
6 at24c1024 1471n?seepr?12/05 device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only dur ing scl low time periods (see figure 4 on page 7). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 5 on page 8). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see figure 5 on page 8). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero during the ninth cl ock cycle to acknowl- edge that it has received each word. standby mode: the at24c1024 features a low-power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. clock up to 9 cycles. 2. look for sda high in each cycle while scl is high. 3. create a start condition. device power up & power down recommendation power up: it is recommended to power up from 0v to full vcc in less than 1ms and then hold for at least 100s at full vcc level before first operation. power down: it is recommended to power down from full vcc to 0v in less than 1ms and then hold at 0v for at least 0.5s before power up. it is not recommended to vcc power down to non-zero volt and then slowly go to zero volt.
7 at24c1024 1471n?seepr?12/05 figure 2. bus timing (scl: serial clock, sda: serial data i/o ? ) figure 3. write cycle timing (scl: serial clock, sda: serial data i/o) note: 1. the write cycle time t wr is the time from a valid stop condition of a write s equence to the end of the internal clear/write cycle. figure 4. data validity t wr (1) stop condition start condition wordn ack 8th bit scl sda
8 at24c1024 1471n?seepr?12/05 figure 5. start and stop definition figure 6. output acknowledge device addressing the 1024k eeprom requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see figure 7 on page 11). the device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. this is common to all two-wire eeprom devices. the 1024k uses the one device address bit, a1, to allow up to two devices on the same bus. the a1 bit must compare to the corresponding hardwired input pin. the a1 pin uses an inter- nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float. the seventh bit (p 0 ) of the device address is a memory page address bit. this memory page address bit is the most significant bit of the data word address that follows. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is not made, the device will retu rn to a standby state. data security: the at24c1024 has a hardware data protection scheme that allows the user to write-protect the entire memory when the wp pin is at v cc .
9 at24c1024 1471n?seepr?12/05 write operations byte write: to select a data word in the 1024k memory requires a 17-bit word address. the word address field consists of the p 0 bit of the device address, then the most significant word address followed by the least significant word address (see figure 8 on page 11) a write operation requires the p 0 bit and two 8-bit data word addresses following the device address word and acknowledgme nt. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a zero. the addressing device , such as a mi crocontroller, then must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (see figure 8 on page 11). page write: the 1024k eeprom is capabl e of 256-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first da ta word is clocked in. instea d, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. the eeprom will respond with a ze ro after each data word receiv ed. the microcontroller must ter- minate the page write sequence with a stop condition (see figure 9 on page 11). the data word address lower 8 bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 256 data words are transmitted to the eeprom, the data word addres s will ?roll over? and previous data will be overwritten. the address ?rollover? during write is from the last byte of the current page to the first byte of the same page. acknowledge polling: once the internally timed write cycle has started and the eeprom inputs are disabled, acknowledge polling c an be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if t he internal write cycle has co mpleted will the eeprom respond with a zero, allowing the read or write sequence to continue.
10 at24c1024 1471n?seepr?12/05 read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word addr ess counter main tains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?rollover? during read is from the last byte of the last memory page, to the first byte of the first page. once the device address with the read/write sele ct bit set to one is clocked in and acknowl- edged by the eeprom, the current address dat a word is serially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condi- tion (see figure 10 on page 11). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address wo rd and data word address are clocked in and acknowledged by the eeprom, the microcontr oller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. th e eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a fol- lowing stop condition (see figure 11 on page 12). sequential read: sequential reads are initiated by either a current address read or a ran- dom address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eepr om receives an ackn owledge, it will cont inue to increment the data word address and serially clock out sequential data words. when the memory address limit is reache d, the data word address will ?roll over? and the sequential read will con- tinue. the sequential read operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop condition (see figure 12 on page 12).
11 at24c1024 1471n?seepr?12/05 figure 7. device address figure 8. byte write figure 9. page write figure 10. current address read 0 significant most significant least p 0 p 0 significant most significant least
12 at24c1024 1471n?seepr?12/05 figure 11. random read figure 12. sequential read p 0 high byte address low byte address p 0 high byte address low byte address data n + 1 data n + 2 data n + x
13 at24c1024 1471n?seepr?12/05 notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics tables. 2. ?u? designates green package & rohs compliant. 3. available in waffle pack and wafer form; order as sl788 for wafer form. bumped die available upon request. please contact serial eeprom marketing. ordering information (1) ordering code package operation range at24c1024c1-10cu-2.7 (2) at24c1024-10pu-2.7 (2) at24c1024w-10su-2.7 (2) at24c1024y4-10yu-2.7 (2) 8cn1 8p3 8s2 8y4 lead-free/halogen-free/ industrial temperature (?40 c to 85 c) at24c1024-w2.7-11 (3) die sale industrial temperature (?40 c to 85 c) package type 8cn1 8-lead, 0.300" wide, leadless array package (lap) 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s2 8-lead, 0.200" wide, plastic gull wing small outline package (eiaj soic) 8y4 8-lead, (6.00 x 4.90 mm body) soic array package (sap) options ?2.7 low voltage (2.7v to 5.5v)
14 at24c1024 1471n?seepr?12/05 packaging information 8cn1 ? lap 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8cn1 , 8-lead (8 x 5 x 1.04 mm body), lead pitch 1.27 mm, leadless array package (lap) a 8cn1 11/13/01 common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.36 0.41 0.46 1 d 7.90 8.00 8.10 e 4.90 5.00 5.10 e 1.27 bsc e1 0.60 ref l 0.62 .0.67 0.72 1 l1 0.92 0.97 1.02 1 note: 1. metal pad dimensions. pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d
15 at24c1024 1471n?seepr?12/05 8p3 ? pdip 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 p 3 , 8 -le a d, 0. 3 00" wide body, pl as tic d ua l in-line p a ck a ge (pdip) 01/09/02 8 p 3 b note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to jedec dr a wing m s -001, v a ri a tion ba, for a ddition a l inform a tion. 2. dimen s ion s a a nd l a re me asu red with the p a ck a ge s e a ted in jedec s e a ting pl a ne g au ge g s - 3 . 3 . d, d1 a nd e1 dimen s ion s do not incl u de mold fl as h or protr us ion s . mold fl as h or protr us ion s s h a ll not exceed 0.010 inch. 4. e a nd ea me asu red with the le a d s con s tr a ined to b e perpendic u l a r to d a t u m. 5. pointed or ro u nded le a d tip s a re preferred to e as e in s ertion. 6. b 2 a nd b3 m a xim u m dimen s ion s do not incl u de d a m ba r protr us ion s . d a m ba r protr us ion s s h a ll not exceed 0.010 (0.25 mm). common dimen s ion s (unit of me asu re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b3 4 plc s a ? ? 0.210 2 a2 0.115 0.1 3 0 0.195 b 0.014 0.01 8 0.022 5 b 2 0.045 0.060 0.070 6 b3 0.0 3 0 0.0 3 9 0.045 6 c 0.00 8 0.010 0.014 d 0. 3 55 0. 3 65 0.400 3 d1 0.005 ? ? 3 e 0. 3 00 0. 3 10 0. 3 25 4 e1 0.240 0.250 0.2 8 0 3 e 0.100 b s c ea 0. 3 00 b s c 4 l 0.115 0.1 3 0 0.150 2 top view s ide view end view
16 at24c1024 1471n?seepr?12/05 8s2 ? eiaj soic 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8s 2 , 8 -le a d, 0.209" body, pl as tic s m a ll o u tline p a ck a ge (eiaj) 10/7/0 3 8s 2 c common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to eiaj dr a wing edr-7 3 20 for a ddition a l inform a tion. 2. mi s m a tch of the u pper a nd lower die s a nd re s in bu rr s a re not incl u ded. 3 . it i s recommended th a t u pper a nd lower c a vitie s b e e qua l. if they a re different, the l a rger dimen s ion s h a ll b e reg a rded. 4. determine s the tr u e geometric po s ition. 5. v a l u e s b a nd c a pply to p b / s n s older pl a ted termin a l. the s t a nd a rd thickne ss of the s older l a yer s h a ll b e 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0. 3 5 0.4 8 5 c 0.15 0. 3 5 5 d 5.1 3 5. 3 5 e1 5.1 8 5.40 2, 3 e 7.70 8 .26 l 0.51 0. 8 5 ? 0 8 e 1.27 b s c 4 end view s ide view e b a a1 d e n 1 c e1 ? l top view
17 at24c1024 1471n?seepr?12/05 8y4 ? sap 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0906 title drawing no. r rev. 8 y4 , 8 -le a d (6.00 x 4.90 mm body) s oic arr a y p a ck a ge ( s ap) y4 a 8 y4 5/24/04 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a ? ? 0.90 a1 0.00 ? 0.05 d 5. 8 0 6.00 6.20 e 4.70 4.90 5.10 d1 2. 8 5 3 .00 3 .15 e1 2. 8 5 3 .00 3 .15 b 0. 3 5 0.40 0.45 e 1.27 typ e1 3 . 8 1 ref l 0.50 0.60 0.70 a e a1 b pin 1 index area d a pin 1 id e1 d1 l e e1
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